1. Field of the Invention
This invention relates generally to the system architecture and data management techniques to configure and design a single chip Ethernet frame switching system. More particularly, this invention relates to an improved system architecture implemented with new techniques of frame data management to reduce the memory requirement on the single chip and to increase the speed of frame switching operations. An Ethernet frame switching system can be built on a single chip with less gate counts while maintaining a high bandwidth switching operation with high port density.
2. Description of the Prior Art
Traditional Ethernet frame-switching systems are designed and manufactured with a technology by storing the incoming data frames into some sort of local buffers before the data frames are forwarded to their destination ports through a switching fabric. This kind of approach usually leads to the application of more complicated frame data management schemes, and requires large number of gate counts for implementing high performance and high port density Ethernet frame switching system. Since the integrated circuits (ICs) designed for conventional Ethernet frame switching system occupy larger areas of silicon wafer, it is difficult to implement a Ethernet frame switching system with high port density and high throughput performance on a single silicon chip to significantly increase the performance/cost ratio.
FIG. 1 shows briefly a system configuration of a conventional Ethernet frame switching system 100. The system is consisted by a set of logical units, wherein each logic unit includes a physical layer device, i.e., PHY 104, a local traffic controllers 101, and a local buffers 102. The frame switching system further includes a switching fabric 103, and a address resolution logic 105. Local traffic controller 101 may contain one or multiple copies of Medium Access Control (MAC) logic circuitry to handle the transmission and reception process of each port. Data frames coming into the frame switching system are forwarded by local traffic controller 101 to their corresponding destination ports through the shared switching fabric 103. Switching fabric 103 can be in the form of a cross-bar switch, a shared bus, or a shared memory. The access to the switching fabric 103 is controlled by an arbitration circuitry to select which local traffic controllers 101 can access the switching fabric. Since the access is arbitrated, there is no guarantee that the data can be forwarded to correspondent destination port within limited time period. Therefore, a conventional frame switching system has to store the ingress data into a local buffer 102 before further processes are carried out to accomplish the switching operations. Local buffer 102 can be in the form of random access memory or deep FIFO. Due to this multiple logic unit architecture and the two tier memories for storing the data frames, more complicated frame data management schemes are required. Integrated circuits of large gate count are employed in order to implement the more complicate data frame management schemes to achieve a high performance and high port density Ethernet frame switching system. Large areas of a silicon wafer are occupied by the integrated circuits thus limiting feasibility in implementing this switching system in a single chip.
Therefore, a need still exists in the art of local area network communication to provide a new and improved system configuration and frame data management techniques for managing the frame switching tasks. It is desirable that an Ethernet frame switching system with high switching throughput performance and high port density can be implemented using limited gate count, whereby the single chip frame switching system can be produced at significant lower cost. In order to reduce the wafer areas occupied by the integrated circuits of the frame switching system, it is further desirable that the local buffer for each port in the switching system can be eliminated. Therefore, the areas occupied by the multiple local buffers for each port are no longer required.
It is therefore an object of the present invention to provide a simplified architecture for an Ethernet frame switching system, designed with assured bandwidth to access the switching fabric, such that the requirement on local buffer of each port can be eliminated and the aforementioned difficulties and limitations in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a simplified architecture for an Ethernet frame switching system by directly writing the incoming data into a shared memory buffer from all the ports and applying a more effective and streamlined global frame management process such that the difficulties of the conventional two-tier memory storage configuration can be overcome.
Another object of the present invention is to provide a simplified architecture for an Ethernet frame switching system without requiring a local buffer for each port by employing a shared global memory for all the ports and applying a more effective and streamlined global frame management process such that the gate count of the switching system can be reduced with less silicon wafer areas occupied by the frame switching system to allow single chip integration of a high performance and high port density frame switching system.
Another object of the present invention is to provide a simplified architecture for an Ethernet frame switching system without requiring a local buffer for each port by employing a shared global memory for all the ports and applying a more effective and streamlined global frame management process such that the system throughput performance can be improved without requiring the use of device of higher clock rate whereby switching device of high performance, high port density and low cost can be achieved.
Another object of the present invention is to provide a simplified architecture for an Ethernet frame switching system with assured bandwidth for all the ports and applying a more effective and streamlined global frame management process such that the throughput of the system is truly non-blocking under any kind of traffic load, and the forwarding rate of the system can be wire speed.
Briefly, in a preferred embodiment, the present invention includes an Ethernet frame switching system for receiving and transmitting data frames from and to a plurality of ports. The frame switching system includes a plurality of port control units for managing the transmission and reception procedural processes with a physical layer device. The frame switching system further includes a queue management unit (QMU) connected with data buses to the port control unit. The data frames received from or transmitted to the port control unit are managed by the QMU that these data frames received are transmitted directly to and data frame for transmission or retrieved directly from a single shared data frame buffer such that the local data frame buffer is not required in each of the port control units. Without these local data buffers, the QMU applies a novel link list queue management process to complete the writing and reading of data frame for transfer over the data bus in a single time-division multiplexed time slot such that no loss of data frame occurs. The data frame queue management further includes a special technique for managing the broadcast frames by employing a broadcast frame counter together with the link list management scheme. The first-in-first-out order is maintained in combination with the unicast frames without requiring multiple data frame storage slots for the broadcasting frames such that high through put of frame switching is achieved without imposing additional memory requirements.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.